Axi Setting Register (Drasr) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
13.6.11

AXI setting register (DRASR)

This register sets AXI interface operation.
Address
Bit 15 14 13
Name - - -
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value X X X
Bit field
No. Name
15-1 (Reserved)
0 CACHE
13-16
12 11 10 9
- - - -
X X X X
Reserved bits.
Write access is ignored.
CACHE
On/Off of cash operation at reading are performed.
0 Cache off (initial value)
1 Cache on
When single reading continuously occurs in a single access (16 byte) to DRAM,
reading operation from AXI is enabled by the cached data in AXI module instead of
accessing to DRAM. However cache is cleared in the following conditions.
•
Burst reading access occurs to AXI bus in DDR2C
•
Write access occurs to AXI bus in DR2C
F300_0000 + 30
H H
8 7 6 5
- - - -
X X X X
Description
4 3 2 1
- - - - CACHE
X X X X
0
0