Display Clock And Timing; Limitations; Dual Display Configuration Example - Fujitsu MB86R02 Jade-D Hardware Manual

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MB86R02 'Jade-D' Hardware Manual V1.64

Display Clock and Timing

It is necessary to supply a display clock of twice the frequency for dual display functionality. VGA

display typically uses a 25MHz display clock in single display mode whereas a 50MHz display clock is

required for dual display mode. The timing parameters such as HTP except the scaling ratio (SC)

should be the same.

The maximum display clock frequency determines the maximum resolution available. For 800 x 480, a

66MHz DCLK clock is required.

For multiplex dual display, two display devices must have the same scan rate and resolution with

common sync signals.

The external sync mode can not be used in multiplex dual display mode.

The external sync mode can not be used together when the TCON of the MB86R02 'Jade-D' TCON is

active. Using external sync mode together with an active TCON creates an instable horizontal back

Single display

In the case of a single display application, set the DEN bit to '1' for the single display controller to be

used. Multiplex dual display mode has to be disabled. The following example shows the settings for

the use of display controller 0 only.

VCCC/dis2s=0

Using display controller 1 instead if of course possible.

Parallel dual display (no multiplex)

In the case of parallel dual display without multiplex, enable the DEN bit for both display controllers.

Multiplex dual display mode has to be disabled.

VCCC/dis2s=0

Multiplex dual display ( internal demultiplex )

In the case of multiplex dual display with an internal demultiplexer, enable the DEN-bit for display

controller 0. Multiplex dual display mode has to be enabled. The multiplexed video stream from