Bus Control Register (I2Cxbcr) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

29.7.3 Bus control register (I2CxBCR)

Address
Bit 31 30 29
Name
R/W R R R
Initial value 0 0 0
Bit 15 14 13
Name
R/W R R R
Initial
valu 0 0 0
e
This is cleared (except bits 7 and 6) when the EN bit of I2CxCCR is "0".
Bit 7: BER (Bus ERror)
This is the bus error interrupt request flag bit.
For writes
BER
0 Bus error interrupt request flag is cleared
1 N/A
For reads
BER
0 Bus error is not detected
1 Incorrect start and stop conditions are detected during data transfer
When this bit is set, the EN bit of the I2CxCCR register is cleared, this module enters the halt state,
and the data transfer is discontinued.
Bit 6: BEIE (Bus Error Interrupt Enable)
This is the bus error interrupt permission bit.
On read/writes
BEIE
0 Bus error interrupt is prohibited
1 Bus error interrupt is permitted
If this bit is "1" and BER bit is "1", an interrupt occurs.
Bit 5: SCC (Start Condition Continue)
This is the start condition generation bit.
At writing
SCC
0 N/A
1 Start condition is generated again on master transfer
This bit is automatically cleared after setting "1".
ch0：FFF5_6000 + 04h ch1：FFF5_7000 + 04h
28 27 26 25
R R R R
0 0 0 0
12 11 10 9
(Reserved)
R R R R
0 0 0 0
24 23 22 21
(Reserved)
R R R R
0 0 0 0
8 7 6 5
BER BEIE SCC MSS
R R/W R/W R/W R/W R/W R/W R/W R/W
0 0 0 0
State
State
State
State
20 19 18 17
R R R R
0 0 0 0
4 3 2 1
ACK GCAA INTE
0 0 0 0
29-9
16
R
0
0
INT
0