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MB86R02 'Jade-D' Hardware Manual V1.64
28.7.3 Example of reception procedure
D at a r eady or l i ne st at us i nt err upt ?
2.
3.
1. When certain interrupt is permitted, interrupt occurrence is able to be confirmed with interrupt
(INTR) pin (at INTR = "H".)
Moreover, it is confirmed by polling NINT bit in the Interrupt ID register (IIR register) (at NINT
= "0".)
2. Type of interrupt is able to be observed by confirming ID0, ID1 and ID2 bit in the Interrupt ID
register.
3. After interrupt type is judged as reception line status interrupt with the process in item 2,
reception error information is able to be acquired by reading the Line status register which
also releases the interrupt (INTR= "L".)
4. After interrupt type is judged as reception data ready interrupt with the process in item 2, read
number of character corresponding to the trigger level to acquire reception character.
Reception data ready status is also able to be confirmed by referring DR bit in the Line status
register. The interrupt is released when data in FIFO becomes less than the trigger level
(INTR= "L".)
28-18
Recept i on pr ocedur e
Li ne st at us i nt er r upt
I nt er r upt f act or check
( r ecept i on er ror f act or )
End
Figure 28-4 Example of reception procedure
I nt er r upt occur s
1.
Recept i on dat a ready i nt er r upt
Readi ng r ecept i on FI FO
4.
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