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MB86R02 'Jade-D' Hardware Manual V1.64
Bit
init
Name
ial
reserved
7
1
reserved
6
1
reserved
5
0
reserved
4
0
reserved
3
0
reserved
2
1
reserved
1
1
reserved
0
1
Table 17-20 TX config_byte_7
Bit
init
Name
ial
cfg_trigger_cycle_length[6]
7
0
cfg_trigger_cycle_length[5]
6
0
cfg_trigger_cycle_length[4]
5
0
cfg_trigger_cycle_length[3]
4
1
cfg_trigger_cycle_length[2]
3
0
cfg_trigger_cycle_length[1]
2
0
cfg_trigger_cycle_length[0]
1
1
reserved
0
0
Table 17-3 TX config_byte_8
config_byte_7
Description
do not change
do not change
do not change
do not change
do not change
config_byte_8
Description
APIX PHY (Soft IP): configures cycle length
of 'sbdown_trigger's pulse pattern
9 : required when operating in Full and Half
Bandwidth Mode
18 : required when operating in Low
Bandwidth Mode 2 (APIX PHY core_clk ==
62.5 MHz)
36 : required when operating in Low
Bandwidth Mode 1 (APIX PHY core_clk ==
62.5 MHz)
36 : required when operating in Low
Bandwidth Mode 2 (APIX PHY core_clk ==
125 MHz)
72 : required when operating in Low
Bandwidth Mode 1 (APIX PHY core_clk ==
125 MHz)
do not change
17-31
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