Fujitsu MB86R02 Jade-D Hardware Manual page 323

MB86R02 'Jade-D' Hardware Manual V1.64
Bit 17 Reserved
Do not modify
Bit 10 R0PXALIGND
rx_pix_aligned, 1=Pixel link operational
Bit 9 Reserved
Do not modify
Bit 8 Reserved
Do not modify
Bit 7 Reserved
Do not modify
Bit 6 Reserved
Do not modify
Bit 5 Reserved
Do not modify
Bit 4 Reserved
Do not modify
Bit 3 Reserved
Do not modify
Bit 2 Reserved
Do not modify
Bit 1 R0PHYDWNRDY
indicates that downstream serial channel (APIX PHY) is operational, While 'PHYDWNRDY' is low AShell can't become TA aligned
('CONNECTED' is low). If the local APIX PHY is not used 'PHYDWNRDY' is forced to '1' (rx_down_ready).
Bit 0 R0PLLGOOD
pll_good (is the same for all Tx/Rx channels)
R0STS1
Register address BaseAddress + 3C
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field name
R/W
Reset value
Channel 0 RX status register 1
Bit 31 - 24 Reserved
Do not modify
Bit 20 - 16 R0Eye
Measured eye opening, 1=edge in this phase during measurement period was set by Eyetime
Bit 15 - 8 R0INSYNC
Synchronisation losses rx_down__sync_loss_cnt
Bit 7 - 0 R0PLLBAD
PLL synchronisation losses pll_bad_cnt
CH1CFG
Register address BaseAddress + 40
Bit number 31 30
R/W RW RW
Reset value 0 0
H H
Channel 1 Config
Bit CH1ENDwnPhy
31 Enable Downstream PHY, 0=power OFF, 1=Power ON
Bit CH1ENUpPhy
30 Enable Upstream PHY, 0=power OFF, 1=Power ON
Bit CH1SDINCDR_Bw
25 - Channel 1 CDR bandwidth control 000 : no tracking 001 : slowest tracking / lowest bandwidth 3FF : fastest tracking / highest bandwidth
16
Bit CH1SDINWindow
12 - Select window for CDR voter 000: 1 clock (last 4 bits) min 2 edges in any 1 phase 001: 2 clocks (last 8 bits) min 3 edges in any 1 phase
10 010: 3 clocks (last 12 bits) min 3 edges in any 1 phase 011: 4 clocks (last 16 bits) min 3 edges in any 1 phase 100: until 2 edges received
in any one phase 101: until 4 edges received in any one phase 110: until 8 edges received in any one phase 111: until 16 edges received
in any one phase
Bit 9 CH1SDIN_Invert
1: Invert data on SDIN pin (PCB optimization)
Bit 8 CH1SDOUT_Invert
1: Invert data on SDOUT pin (PCB optimization)
Bit 6 CH1UpNomSwing
- 3 Transmit swing (binary coded, 1 LSB = 0.53mA) 0000: min 4mA, 0001: 4.53mA, ..., 1111: max 12mA,
Bit 2 Reserved
Do not modify
Bit 1 Reserved
17-10
H
Reserved
R
0
H
H
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RW
0
H
R0Eye R0INSYNC
R R
X 0
H
9
RW RW
6 0
H H
R0PLLBAD
R
0
H
8 7 6 5 4 3 2 1 0
RW RW RW RW
0 F 0 1
H H H H