Adcx Status Register (Adcxstatus) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
26.9.7

ADCx status register (ADCxSTATUS)

This register is to indicate whether A/D data conversion is completed.
instance 0：FFF5_2000 + 14
Address
instance 1：FFF5_3000 + 14
Bit 31 30 29
Name
R/W R0 R0 R0
Initial value 0 0 0
Bit 15 14 13
Name
R/W R0 R0 R0
Initial value 0 0 0
Bit field
Description
No. Name
31-2 (Reserved) It is a reserved bit.
Write access is ignored. Read value of these bits is always "0".
1 CMP1 Whether A/D data conversion is completed for input 1 is indicated.
At the time data is set to ADCxDATA, CMP bit becomes "1".
Writing "0" to the bit clears register value (although "1" is written to CMP bit, register bit value
does not change.)
Setting "1" to CMP bit outputs interrupt.
0 CMP0 Whether A/D data conversion is completed for input 0 is indicated.
At the time data is set to ADCxDATA, CMP bit becomes "1".
Writing "0" to the bit clears register value (although "1" is written to CMP bit, register bit value
does not change.)
Setting "1" to CMP bit outputs interrupt.
26-10
H
H
28 27 26 25
R0 R0 R0 R0
0 0 0 0
12 11 10 9
(Reserved)
R0 R0 R0 R0
0 0 0 0
0 A/D data conversion is not completed (initial value)
1 A/D data conversion is completed
0 A/D data conversion is not completed (initial value)
1 A/D data conversion is completed
24 23 22 21
(Reserved)
R0 R0 R0 R0
0 0 0 0
8 7 6 5
R0 R0 R0 R0
0 0 0 0
20 19 18 17
R0 R0 R0 R0
0 0 0 0
4 3 2 1
CMP
CMP1
R0 R0 R0 R/W0 R/W0
0 0 0 0
16
R0
0
0
0
0