Jade-D Restrictions - Fujitsu MB86R02 Jade-D Hardware Manual

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MB86R02 'Jade-D' Hardware Manual V1.64

Jade-D Restrictions

Only a single channel video interface is supported by one APIX PHY.

Low Bandwidth Mode1 at 250 Mbit/s and Low Bandwidth Mode 2 at 125 Mbit/s are available

via the APIX side band channel only. Therefore it is not possible to transfer pixel data in both

Low Bandwidth modes.

Please note that the application software can not use the PLL_GOOD register to correctly

evaluate the status of the APIX PLL if separate ECLK and XTAL clock sources are used for

the core and APIX units respectively. The internal signal 'pll_good', which sets the

PLL_GOOD register is not cleared if the external XTAL0 and XTAL1 clocks are stopped.