Axi Priority Setting Register (Caxi_Ps) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

7.4.11 AXI priority setting register (CAXI_PS)

Sets the priority level of the AXI interconnect bus. Use the bitfield to set a priority level in the range of
0 ... 4. Do not set a value of 5 or more. If you do so, the write will be ignored and the previous value
maintained.
Address
Bit 31 30 29
Name (Reserved)
R/W R R R
Initial value 0 0 0
Bit 15 14 13
Name (Reserved) P_SEL3
R/W R R/W R/W
Initial value 0 1 0
Bit field
Number Name
31-19 (Reserved)
18-16 P_SEL4
(Priority Select4)
15 (Reserved)
14-12 P_SEL3
(Priority Select3)
11 (Reserved)
10-8 P_SEL2
(Priority Select2)
FFF4_2000 + 2Ch
28 27 26 25
R R R R
0 0 0 0
12 11 10 9
(Reserved) P_SEL2
R/W R R/W R/W
0 0 0 1
Reserved
Writes are ignored. Reads will return a '0' at all times.
The priority level of AXI interconnect bus can be set by this bitfield.
000 0
001 1
010 2
011 3
100 4 (initial value)
Reserved
Writes are ignored. Reads will return a '0' at all times.
The priority level of AXI interconnect bus can be set by this bit.
000 DispCap
001 AHB
010 CPU
011 HBUS(initial value)
100 DRAW
Reserved
Writes are ignored. Reads will return a '0' at all times.
The priority level of AXI interconnect bus can be set by this bit.
000 DispCap
001 AHB
010 CPU(initial value)
011 HBUS
24 23 22 21
R R R R R
0 0 0 0
8 7 6 5
(Reserved) P_SEL1
R/W R R/W R/W
0 0 0 0
Function
20 19 18 17
P_SEL4
R R/W R/W
0 0 1 0
4 3 2 1
(Reserved) P_SEL0
R/W R R/W R/W
1 0 0 0
16
R/W
0
0
R/W
0
7-17