Interrupt Status Register (Cist) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

7.4.4 Interrupt status register (CIST)

Address
Bit 31 30 29
Name INT31 (Reserved)
R/W R/W R/W R/W
Initial value 0 0 0
Bit 15 14 13
Name (Reserved)
R/W R/W R/W R/W
Initial value 0 0 0
Bit field
Number Name
31 INT31
(MediaLB DINT)
30-29 (Reserved)
28 INT28
(HBUS2AXI)
27 INT27 (MBUS2AXI
(Draw))
26 INT26 (MBUS2AXI
(DispCap))
25 INT25
(AHB2AXI
(CPUroot))
FFF4_2000 + 10h
28 27 26 25
INT28 INT27 INT26 INT25
R/W R/W R/W R/W
0 0 0 0
12 11 10 9
R/W R/W R/W R/W
0 0 0 0
This bit is set to '1' if i_int31 becomes '1'.
Clearing is done by writing a '0' to this bit.
If Bit31 of the INT Mask register is set to mask "0", this bit is fixed at "0".
0 There is no interrupt. (initial value)
1 There is an interruption.
Reserved
Writes are ignored. Reads will return a '0' at all times.
This bit is set to '1' if i_int28 becomes '1'.
Clearing is done by writing a '0' to this bit.
If Bit28 of the INT Mask register is set to mask "0", this bit is fixed at "0".
0 There is no interrupt. (initial value)
1 There is an interruption.
This bit is set to '1' if i_int27 becomes '1'.
Clearing is done by writing a '0' to this bit.
If Bit28 of the INT Mask register is set to mask "0", this bit is fixed at "0".
0 There is no interrupt. (initial value)
1 There is an interruption.
This bit is set to '1' if i_int26 becomes '1'.
Clearing is done by writing a '0' to this bit.
If Bit26 of the INT Mask register is set to mask "0", this bit is fixed at "0".
0 There is no interrupt. (initial value)
1 There is an interruption.
This bit is set to '1' if i_int25 becomes '1'.
Clearing is done by writing a '0' to this bit.
If Bit25 of the INT Mask register is set to mask "0", this bit is fixed at "0".
24 23 22 21
INT24 (Reserved)
R/W R/W R/W R/W
0 0 0 0
8 7 6 5
INT5
R/W R/W R/W R/W
0 0 0 0
Function
20 19 18 17
R/W R/W R/W R/W
0 0 0 0
4 3 2 1
(Reserved)
R/W R/W R/W R/W
0 0 0 0
16
R/W
0
0
R/W
0
7-7