Fujitsu MB86R02 Jade-D Hardware Manual page 197

MB86R02 'Jade-D' Hardware Manual V1.64
Routine to clear interrupt factor
M
OV R1, #0
LDR R0, = IRQF
STR R1, [R0];
begins. .
LOOP
LDR R1,[R0]
CMP R1,#0
BNE LOOP
;; Clear ARM IRQ Flag →Enable Intrrupt
MRS R2, CPSR
BIC R2, R2, #I_Bit
MSR CPSR_c, R2;
Move to the corresponding interrupt handler when IRQ interrupt that is higher than a current IRQ
source occurs.
Main routine for this interrupt factor
M
RS R2, CPSR
ORR R2, R2 #1_Bit
MSR CPSR_c, R2;
LDR R0, = ILM
LDMFD SP!, {R1, R2}
MSR SPSR_cxsf, R2
STR R1, [R0];
[ma].
LDMFD SP! {R0-R12, R14};
SUBS PC, R14, #4;
; IRQF bit (bit 0) of the IRQF register is clear.
;The decision operation of the following interrupt level
; IRQF clear flag confirmation.
;Clear I bit of the CPSR register (It is included in the core).
The IRQ interrupt is made valid (enable).
;Set I bit of the CPSR register (It is included in the core).
Make the IRQ interrupt invalidity (disable).
;It is preserved ..(of ILM and the SPSR_irq register.. ..core.. ..content..
Return the value of [reteiru]).
;Return the register value.
;CPSR < - SPSR_irq, PC < - R14 -4
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