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MB86R02 'Jade-D' Hardware Manual V1.64
9.5.3 IRQ mask register (IRQM)
The IRQM register controls the mask of the assert of the IRQ interrupt.
Address
FFFF_FE00
Bit
31
30
29
Name
-
-
-
R/W
R/W
R/W
R/W
Initial value
X
X
X
Bit
15
14
13
Name
-
-
-
R/W
R/W
R/W
R/W
Initial value
X
X
X
Bit field
Number
Name
31-1
-
0
IRQM
9.5.4 Interrupt level mask register (ILM)
The ILM register sets the interrupt level said to be valid from the ARM core. The interrupt controller
notifies the ARM core the IRQ interrupt when the IRQ interrupt source is larger than the set value of
this register.
" Interrupt level of ICR register > Interrupt level of ILM register" -> Generated IRQ interrupt
Address
FFFF_FE00
Bit
31
30
29
Name
-
-
-
R/W
R/W
R/W
R/W
Initial value
X
X
X
Bit
15
14
13
Name
-
-
-
R/W
R/W
R/W
R/W
Initial value
X
X
X
Bit field
Number
Name
9-16
IRC0:
or FFFE_8000
+ 04
H
H
H
28
27
26
25
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
12
11
10
9
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
It is an unused bit.
The write access is ignored. The read value of these bits is undefined.
The mask does the assert of the IRQ interrupt.
0 The assert of IRQ can certain the mask.
1 The assert of IRQ is valid.
This bit is initialized by reset by "0".
IRC0:
or FFFE_8000
+ 08
H
H
H
28
27
26
25
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
12
11
10
9
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
IRC1: FFFB_0000
IRC2: FFFB_1000
24
23
22
21
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
8
7
6
5
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
Explanation
IRC1: FFFB_0000
IRC2: FFFB_1000
24
23
22
21
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
8
7
6
5
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
Explanation
+ 04
H
H
+ 04
H
H
20
19
18
17
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
4
3
2
1
-
-
-
-
IRQM
R/W
R/W
R/W
R/W
X
X
X
X
+ 08
H
H
+ 08
H
H
20
19
18
17
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
4
3
2
1
-
ILM3 ILM2 ILM1
R/W
R/W
R/W
R/W
X
1
1
1
16
-
R/W
X
0
R/W
0
16
-
R/W
X
0
ILM0
R/W
1
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