Registers; Register List - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
25.7

Registers

This section describes the PWM registers.
25.7.1

Register list

This LSI has 2 PWM channels and each has the registers shown in Table 14-1.
Table 25-1 PWM register list
Address
Channel
Base
PWM ch0 FFF4_1000
H
PWM ch2 FFF4_6000
H
PWM ch4 FFF4_7000
H
PWM ch6 FFF4_8000
H
(Output pin
PWM_O0,
PWM_O2,
PWM_O4,
PWM_O6)
PWM ch1 FFF4_1100
H
PWM ch3 FFF4_6100
H
PWM ch5 FFF4_7100
H
PWM ch7 FFF4_8100
H
(Output pin
PWM_O1,
PWM_O3,
PWM_O5,
PWM_O7)
Note:
Access PWM ch0 and PWM ch1 areas with 32 bits (word).
Register
Offse
t
+ 00 PWM ch0 base clock
H
register
+ 04 PWM ch0 pulse width
H
register
+ 08 PWM ch0 phase register PWM0PR
H
+ 0C PWM ch0 duty register
H
+ 10 PWM ch0 status register PWM0CR
H
+ 14 PWM ch0 start register
H
+ 18 PWM ch0 current count
H
register
+ 1C PWM ch0 interrupt
H
register
+ 00 PWM ch1 base clock
H
register
+ 04 PWM ch1 pulse width
H
register
+ 08 PWM ch1st place aspect
H
register
+ 0C PWM ch1 duty register
H
+ 10 PWM ch1 status register PWM1CR
H
+ 14 PWM ch1 start register
H
+ 18 PWM ch1 current count
H
register
+ 1C PWM ch1 interrupt
H
register
Abbreviatio
n
PWM0BCR Setting base clock of PWM cycle
PWM0TPR Setting cycle length of 1 pulse
Setting phase cycle of the pulse
PWM0DR Setting duty cycle of the pulse
Setting PWM such as pulse output
format and polarity
PWM0SR Setting start/stop of PWM
PWM0CCR Indicating current count value in the
BASECLK base
PWM0IR Selecting cause of PWM interrupt factor
PWM1BCR Setting base clock of PWM cycle
PWM1TPR Setting cycle length of 1 pulse
PWM1PR Setting phase cycle of the pulse
PWM1DR Setting duty cycle of the pulse
Setting PWM such as pulse output
format and polarity
PWM1SR Setting start/stop of PWM
PWM1CCR Indicating current count value in the
BASECLK base
PWM1IR Selecting cause of PWM interrupt factor
Description
25-3