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MB86R02 'Jade-D' Hardware Manual V1.64
15.7.4.2
Error
When the DMAC receives an error reply from an AHB slave during DMA transfer, it negates the
bus request and immediately stops the transfer even though it has not been completed.
In this case, neither the Block/Transfer count register nor the Source/Destination address
registers are updated.
15-34
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