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MB86R02 'Jade-D' Hardware Manual V1.64
Bit
init
Name
ial
cfg_sbup_dwidth
7
1
cfg_sbup_daclk
6
0
cfg_sbdown_dwidth
5
1
cfg_sbdown_daclk[1]
4
0
cfg_sbdown_daclk[0]
3
0
cfg_ephy
2
0
cfg_eshell
1
1
cfg_mode_sb
0
0
Table 17-25 TX config_byte_shell2
17-36
config_byte_shell2
Description
AShell: enable sbup ports
1: sbup_data[1:0]
0: sbup_data[0]
AShell: validate sbup_data with
1: sbup_data[1]
0: sbup_valid
AShell: enable sbdown ports
1: sbdown_data[1:0]
0: sbdown_data[0]
AShell: generate sbdown clock and transmit as
sbdown_data[1]
11: disable
10: with use of internal counter (asynchronous
to core_clk of APIX PHY)
01: with use of sbdown_trigger (synchronous to
core_clk of APIX PHY)
00: disable
AShell: connect internal Ashell to external APIX
PHY through GPIO interface
1: enable
0: disable
AShell: connect internal APIX PHY to external
AShell through GPIO interface
1: enable
0: disable
AShell: selects between two different sideband
transmission modes
0: mode0: see Figure 17-28 Mode 0 )
1: mode1: see Figure 17-29 Mode
bandwidth has to be set with
cfg_sbdown_daclk_clength
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