Fujitsu MB86R02 Jade-D Hardware Manual page 751

MB86R02 'Jade-D' Hardware Manual V1.64
Transfer Operation
setting
Abnor
mality
Note:
1. TXDIS and RXDIS are for setting to enable and disable transmission/reception of CNTREG register.
2. start, TXENB, and RXENB are operation control bits of OPRREG register.
3. Empty frame bit is determined by MSKB of CNTREG register.
27-24
Master mode (MSMD = 1)
When reading to transmission FIFO occurs
with having it empty, empty frame is
output. When writing to transmission
FIFO occurs with having it full, set TXOVR
to "1".
Slave mode (MSMD = 0)
When reading to transmission FIFO occurs
with having it empty, empty frame is
output. However do not set TXUDR to "1"
for the 1st output frame after bit becomes
Start = "1" and TXENB = "1".
When writing to transmission FIFO occurs
with having it full, set TXOVR to "1".
If it is not input with the frame rate defined
frame synchronous signal in the
free-running mode, set FERR bit of the
register to "1".
If the next frame synchronous signal is
input before completing 1 frame
transmission in the burst mode, set FERR
bit of the register to "1"