Fujitsu MB86R02 Jade-D Hardware Manual page 22

MB86R02 'Jade-D' Hardware Manual V1.64
29.7.8 Expansion CS register (I2CxECSR) ........................................................................... 29-18
29.7.9 Bus clock frequency register (I2CxBCFR) .................................................................. 29-20
29.8 Operation ........................................................................................................................ 29-21
29.8.1 Start condition ............................................................................................................. 29-21
29.8.2 Stop condition ............................................................................................................. 29-22
29.8.3 Addressing .................................................................................................................. 29-23
29.8.4 Synchronous arbitration of SCL .................................................................................. 29-25
29.8.5 Arbitration .................................................................................................................... 29-26
29.8.6 Acknowledge/Negative acknowledge ......................................................................... 29-27
29.8.7 Bus error ..................................................................................................................... 29-28
29.8.8 Initialization ................................................................................................................. 29-29
29.8.9 One byte transfer from master to slave ...................................................................... 29-30
29.8.10 One byte transfer from slave to master ................................................................... 29-31
29.8.11 Resume from bus error ........................................................................................... 29-32
29.8.12 Interrupt process and wait request operation to master ......................................... 29-33
29.9 Notes .............................................................................................................................. 29-33
30 Serial Peripheral Interface (SPI) .............................................................................................. 30-1
30.1 Outline .............................................................................................................................. 30-1
30.2 Features ........................................................................................................................... 30-1
30.3 Block diagram ................................................................................................................... 30-2
30.4 Supply clock ..................................................................................................................... 30-2
30.5 Transition state ................................................................................................................. 30-3
30.6 Registers .......................................................................................................................... 30-4
30.6.1 Register list ................................................................................................................... 30-4
30.6.2 SPI control register (SPInCR) ....................................................................................... 30-6
30.6.3 SPI slave control register (SPInSCR) ........................................................................... 30-8
30.6.4 SPI data register (SPInDR) ......................................................................................... 30-11
30.6.5 SPI status register (SPInSR) ...................................................................................... 30-12
30.7 Setup procedure flow ..................................................................................................... 30-13
31 CAN Interface (CAN) ............................................................................................................... 31-1
31.1 Outline .............................................................................................................................. 31-1
31.2 Block diagram ................................................................................................................... 31-1
31.3 Supply clock ..................................................................................................................... 31-2
31.4 Registers .......................................................................................................................... 31-2
32 MediaLB Interface .................................................................................................................... 32-1
32.1 Outline .............................................................................................................................. 32-1
32.2 Block diagram ................................................................................................................... 32-1
32.3 Supply clock ..................................................................................................................... 32-2
32.4 Registers .......................................................................................................................... 32-2
33 SD Memory Controller (SDMC) ............................................................................................... 33-1
34 Electrical Characteristics ......................................................................................................... 34-1
34.1 Maximum Ratings ............................................................................................................. 34-1
34.2 Recommended Operating Conditions .............................................................................. 34-2
34.3 Precautions at Power On ................................................................................................. 34-3
34.3.1 Recommended Power On/Off Sequence ..................................................................... 34-3
34.3.2 Power On Reset............................................................................................................ 34-4
34.4 DC Characteristics ........................................................................................................... 34-5
34.4.1 3.3V Standard CMOS I/O ............................................................................................. 34-5
34.4.1.1 3.3V Standard CMOS I/O V-I Characteristic (Driving Capability 1)....................... 34-7
34.4.1.2 3.3V Standard CMOS I/O V-I Characteristic (Driving Capability 2)....................... 34-8
34.4.1.3 3.3V Standard CMOS I/O V-I Characteristics (Driving Capability 3) ..................... 34-9
34.4.2 DDR2SDRAM IF I/O (SSTL_18)................................................................................. 34-10