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MB86R02 'Jade-D' Hardware Manual V1.64
5.1.3.
Watchdog timer control register (CRWR)
This register controls watchdog timer.
Address
Bit
31
30
29
Name
–
–
–
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
X
X
X
Bit
15
14
13
Name
R/W
R0
R0
R0
Initial value
0
0
0
*: Do not set "1" to bit 5
Bit field
No.
Name
31-16
–
15-8
(Reserved)
7
ERST
6
(Reserved)
5
(Reserved)
4
TBR
3
WDRST
FFFE_7000
28
27
26
25
–
–
–
–
X
X
X
X
12
11
10
9
(Reserved)
R0
R0
R0
R0
0
0
0
0
Unused bits.
Write access is ignored, and read value of these bits is undefined.
Reserved bits.
Write access is ignored, and read value of these bits is always "0".
Internal reset of ERSTn monitoring
This bit monitors internal signal of ERSTn.
0
ERSTn is asserted
1
ERSTn is cancelled (initial value)
The initial value of this bit is set to 1 by falling edge of ERSTn., and writing "1" is
ignored.
This bit is set by ERSTn.
Reserved bits.
Write access is ignored, and read value of these bits is always "0".
Reserved bit, always write 0.
Read value of this bit is always "0".
Time based timer reset request
This bit resets the time based timer, and its reset signal is asserted during 1 cycle of
APB clock.
0
Time based timer is not reset (initial value)
1
Reset the time based timer
Writing 0 is ignored.
Watchdog reset monitoring
This bit monitors watchdog reset.
0
Watchdog reset is not asserted
1
Watchdog reset is asserted
The initial value of this bit is undefined, and writing 1 is ignored.
When watchdog is reset, this bit is set to "1".
+ 08
H
H
24
23
22
21
–
–
–
–
X
X
X
X
8
7
6
5
ERS
(Reserved)
TBR WDRST
T
R0/W0
R0 R/W0 R0
R/W1 R/W0 R/W1 R/W R/W
*
0
1
0
0
Description
20
19
18
17
–
–
–
–
X
X
X
X
4
3
2
1
WDTSET
/WDTCL
WDTMODE[1:0]
R
0
X
0
0
5-21
16
–
X
0
0
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