Limitations; Initialization Procedure - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
19.2.4 Register Description
ColourIndex[0...255]
BaseAddress + 0
Register address :
BaseAddress + 3FF
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Field name
R/W
Reset value
Lookuptable for colour indexing, restriction: only 32bit word access is supported
Bit 29 - 20 BlueColourComponentValue
Bit 19 - 10 GreenColourComponentValue
Bit 9 - 0 RedColourComponentValue
CLUTControl
Register address BaseAddress + 400
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Field name
R/W
Reset value
Colour Lookuptable Control
Bit 8 clut_index
Sets the index mode, 0b=disabled, 1b=enabled
Bit 0 clut_bypass
Bypass for Colour Lookuptable, 0b=bypass disable, 1b=bypass enable

19.3 Limitations

A duplicate block RAM does not exist to avoid visible artifacts during the reconfiguration of the color
block RAM when the video frame is active.
It is therefore strongly recommended to modify the CLUT content only during the vertical blanking
period (or by turning off the display during the reconfiguration).
Note also, that the internal bypass functionality of the CLUT module is effectively immediately when the
corresponding register is written (there is no synchronization with the vertical blanking period for
example).
To addressrange 0h ... 3FFh (embedded memory) only word access is supported. Byte or halfword
access is not allowed to this address range.

19.4 Initialization procedure

•
Program 3 CLUT for Red-, Green- and Blue channel
•
Optional: enable index mode
•
Enable CLUT by setting clut_bypass to 0. Otherwise the video input will be bypassed to the
output.
In case the CLUT is enabled, it's strongly recommended to enable the dither-unit to avoid artifacts
generally caused by the quantization of the power function in the area of zero.
19-4
H
H
BlueColourComponentValue
RW
X
H
GreenColourComponentValue
RW
X
clut_index
8 7 6 5 4 3 2 1
RedColourComponentValue
RW
X
8 7 6 5 4 3 2 1 0
clut_bypass
RW RW
0 1
H H
0