Pwmx Current Count Register (Pwmxccr) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
25.7.8

PWMx current count register (PWMxCCR)

This register is to indicate current count value in BASECLK base.
Address
Bit 31 30 29
Name
R/W R R R
Initial value 0 0 0
Bit 15 14 13
Name
R/W R R R
Initial value X X X
Bit field
No. Name
31-16 (Reserved)
15-0 CCR
ch0：FFF4_1000 + 18
ch1：FFF4_1100 + 18
ch2：FFF4_6000 + 18
ch3：FFF4_6100 + 18
ch4：FFF4_7000 + 18
ch5：FFF4_7100 + 18
ch6：FFF4_8000 + 18
ch7：FFF4_8100 + 18
28 27 26 25
R R R R
0 0 0 0
12 11 10 9
R R R R
X X X X
Reserved bits.
Write access is ignored. The read value of these bits is always "0".
Current count value in BASECLK base is indicated.
CCR[15:0] Duty cycle
0 0 BASECLK
1 1 BASECLK
|
65535 65535 BASECLK
H
H
H
H
H
H
H
H
24 23 22 21
(Reserved)
R R R R
0 0 0 0
8 7 6 5
CCR[15:0]
R R R R
X X X X
Description
|
20 19 18 17
R R R R
0 0 0 0
4 3 2 1
R R R R
X X X X
25-11
16
R
0
0
R
X