Outline; Operation - Fujitsu MB86R02 Jade-D Hardware Manual

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MB86R02 'Jade-D' Hardware Manual V1.64

27.7.1 Outline

This module is synchronous serial interface which enables full duplex and multiplexer channel.

It is also able to correspond to various frame formats by register setting.

(Refer to "27.7.3 Frame construction" for detail.)

This module is also able to operate as master and slave. In the master mode, clock (I2S_SCKx)

and frame synchronous signal (I2S_WSx) are output to the external slave. In the slave mode,

they are input from the external master.

During the master mode, I2S_SCKx clock can be output by dividing external clock (I2S_external

clock x) or internal clock (it is selectable at register). Frame synchronous signal can be

generated by free-running or burst mode (generated only when there is transmission data.)

This module equips transmission/reception FIFO, and its depth varies depending on mode:

transmission only mode is 36 word × 32 bit constructive transmission FIFO and reception only

mode is 66 word × 32 bit constructive reception FIFO. Refer to "27.7.3 Frame construction" for

more detail.

Internal transfer between transmission and reception FIFO and internal system memory is able to

be performed by DMA, interrupt, and polling.