I2Sxintcnt Register - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
27.6.11

I2SxINTCNT register

Address
Bit 31 30 29
Name – TXUD1M TBERM FERRM TXUD0M TXOVM TXFDM
R/W R R/W R/W R/W R/W R/W R/W
Initial 0 1 1
Bit 15 14 13
Name (Reserved)
R/W R R R
Initial 0 0 0
Bit field
No. Name
31 (Reserved) Reserved bits.
The write access is ignored. The read value of these bits is always "0".
30 TXUD1M This is transmission FIFO underflow interrupt mask bit.
It becomes "1" by software reset.
29 TBERM This is interrupt mask bit of block size error of transmission channel.
It becomes "1" by software reset.
28 FERRM This is frame error interrupt mask bit.
It becomes "1" by software reset.
27 TXUD0M This is transmission FIFO underflow interrupt mask bit.
It becomes "1" by software reset.
26 TXOVM This is transmission FIFO overflow interrupt mask bit.
It becomes "1" by software reset.
25 TXFDM This is DMA request mask register bit.
It becomes "1" by software reset.
27-16
ch0：FFEE_0020 (h)
28 27 26 25
1 1 1 1
12 11 10 9
TFTH
R R/W R/W R/W
0 0 0 0
0 Interrupt to CPU by TXUDR1 of STATUS register is not masked
1 Interrupt to CPU by TXUDR1 of STATUS register is masked
0 Interrupt to CPU by TBERR of STATUS register is not masked
1 Interrupt to CPU by TBERR of STATUS register is masked
0 Interrupt to CPU by FERR of STATUS register is not masked
1 Interrupt to CPU by FERR of STATUS register is masked.
0 Interrupt to CPU by TXUDR0 of STATUS register is not masked.
1 Interrupt to CPU by TXUDR0 of STATUS register is masked.
0 Interrupt to CPU by TXOVM of STATUS register is not masked.
1 Interrupt to CPU by TXOVM of STATUS register is masked.
0 DMA transfer is requested when reception data written to transmission
FIFO is threshold value or more
1 DMA transfer is not requested even reception data written to transmission
FIFO is threshold value or more
24 23 22 21
TXFIM (Reserved) RBERM RXUDM RXOVM EOPM RXFDM RXFIM
R/W R R R/W R/W R/W
1 0 0 1
8 7 6 5
(Reserved) RPTMR
R/W R R R/W R/W R/W
0 0 0 0
Description
20 19 18 17
R/W R/W R/W
1 1 1 1
4 3 2 1
RFTH
R/W R/W R/W
0 0 0 0
16
1
0
0