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MB86R02 'Jade-D' Hardware Manual V1.64
LSA (displayList Source Address)
Register
HostBaseAddress + 40
address
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
Reserved
R/W
Initial value
This register sets the DisplayList transfer source address. When DisplayList is transferred from
Graphics Memory, set the transfer start address of DisplayList stored in Graphics Memory. Since
the lower two bits of this register are always treated as "0", DisplayList must be 4-byte aligned. The
values set at this register do not change during or after transfer.
LCO (displayList Count)
Register
HostBaseAddress + 44
address
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
Reserved
R/W
Initial value
This register sets the DisplayList transfer count. Set the display list transfer count by the long word.
When "1h" is set, 1-word data is transferred. When "0" is set, it is considered to be the maximum
count and 16M (16,777,216) words of data are transferred. The values set at this register do not
change during or after transfer.
LREQ (displayList transfer REQuest)
Register
HostBaseAddress + 48
address
Bit number
7
Bit field name
R/W
Initial value
This register triggers DisplayList transfer from the Graphics Memory. Transfer is started by setting
LREQ to "1". The DisplayList is transferred from the Graphics Memory to the internal display list
FIFO. Access to the display list FIFO by the CPU or DMA is disabled during transfer.
18-248
H
R0
0
H
R0
0
H
6
5
Reserved
LSA
RW
Don't care
LCO
RW
Don't care
4
3
2
R0
0
R0
0
1
0
LREQ
RW1
0
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