Registers; Register List - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

28.6 Registers

This section describes UART interface module's registers.

28.6.1 Register list

The LSI has 6 UART channels (please note that some are only available via pin multiplex
settings). Each module has the registers shown in Table 28-1.
Table 28-1 UART register list
Channel Address
UART ch0 FFFE1000h
FFFE1004h
FFFE1008h
FFFE100Ch URT0LCR
FFFE1010h
FFFE1014h
FFFE1018h
UART ch1 FFFE2000h
FFFE2004h
FFFE2008h
FFFE200Ch URT1LCR
FFFE2010h
FFFE2014h
FFFE20
18h
UART ch2 FFF50000h
FFF50004h
FFF50008h
FFF5000Ch
FFF50010h
FFF50014h
FFF50018h
UART ch3 FFF51000h
Register
URT0RFR Reception FIFO register (read only) that is valid in DLAB = 0
URT0TFR Transmission FIFO register (write only) that is valid in DLAB = 0
URT0DLL Divider latch (low order byte) register that is valid in DLAB = 1
URT0IER Interrupt enable that is valid in DLAB = 0.
URT0DLM Divider latch (high order byte) register that is valid in DLAB = 1
URT0IIR Interrupt ID register (read only)
URT0FCR FIFO control (write only)
Line control register
URT0MCR Modem control register
URT0LSR Line status register (read only)
URT0MSR Modem status register (read only)
URT1RFR Reception FIFO register (read only) that is valid in DLAB = 0
URT1TFR Transmission FIFO register (write only) that is valid in DLAB = 0
URT1DLL Divider latch register (low order byte) that is valid in DLAB = 1
URT1IER Interrupt enable that is valid in DLAB = 0.
URT1DLM Divider latch (high order byte) register that is valid in DLAB = 1
URT1IIR Interrupt ID register (read only)
URT1FCR FIFO control (write only)
Line control register
URT1MCR Modem control register
URT1LSR Line status register (read only)
URT1M
Modem status register (read only)
SR
URT2RFR Reception FIFO register (read only) that is valid in DLAB = 0
URT2TFR Transmission FIFO register (write only) that is valid in DLAB = 0
URT2DLL Divider latch (low order byte) register that is valid in DLAB = 1
URT2IER Interrupt enable that is valid in DLAB = 0.
URT2DLM Divider latch (high order byte) register that is valid in DLAB = 1
URT2IIR Interrupt ID register (read only)
URT2FCR FIFO control (write only)
URT2LCR Line control register
URT2MCR Modem control register
URT2LSR Line status register (read only)
URT2MSR Modem status register (read only)
URT3RFR Reception FIFO register (read only) that is valid in DLAB = 0
URT3TFR Transmission FIFO register (write only) that is valid in DLAB = 0
Description
28-3