Adcx Clock Selection Register (Adcxcksel) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
instance 0：FFF5_2000 + 08
Address
instance 1：FFF5_3000 + 08
Bit 31 30 29
Name
R/W R0 R0 R0
Initial value 0 0 0
Bit 15 14 13
Name
R/W R0 R0 R0
Initial value 0 0 0
Bit field
No. Name
31-1 (Reserved)
0 XPD
26.9.6

ADCx clock selection register (ADCxCKSEL)

This register is to se to specify ADC clock frequency supplying to A/D converter.
This setting enables sampling plate change.
instance 0：FFF5_2000 + 10
Address
instance 1：FFF5_3000 + 10
Bit 31 30 29
Name
R/W R0 R0 R0
Initial value 0 0 0
Bit 15 14 13
Name
R/W R0 R0 R0
Initial value 0 0 0
Bit field
No. Name
31-3 (Reserved)
26-8
H
H
28 27 26 25
R0 R0 R0 R0
0 0 0 0
12 11 10 9
R0 R0 R0 R0
0 0 0 0
Description
It is a reserved bit.
Write access is ignored. Read value of these bits is always "0".
A/D converter operation is controlled.
0 Power down mode (initial value)
1 Release of power down mode
When "1" is written to XPD bit, A/D converter's power-down mode is released and A/D
data polling starts. Writing "0" to the bit sets A/D converter's power-down mode and A/D
data polling stops.
H
H
28 27 26 25
R0 R0 R0 R0
0 0 0 0
12 11 10 9
(Reserved)
R0 R0 R0 R0
0 0 0 0
Description
It is a reserved bit.
Write access is ignored. Read value of these bits is always "0".
24 23 22 21
(Reserved)
R0 R0 R0 R0
0 0 0 0
8 7 6 5
(Reserved)
R0 R0 R0 R0
0 0 0 0
24 23 22 21
(Reserved)
R0 R0 R0 R0
0 0 0 0
8 7 6 5
R0 R0 R0 R0
0 0 0 0
20 19 18 17
R0 R0 R0 R0
0 0 0 0
4 3 2 1
XPD
R0 R0 R0 R0 R/W
0 0 0 0
20 19 18 17
R0 R0 R0 R0
0 0 0 0
4 3 2 1
CKSEL[2:0]
R0 R0 R/W R/W R/W
0 0 0 0
16
R0
0
0
0
16
R0
0
0
0