Initram Control - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
A software reset occurs by writing "1" to the SWRSTREQ bit of the reset/standby control
register (CRSR). It does not change the state to PLL oscillation stabilization even if the
PLLBYPASS bit of the PLL control register (CRPR) is "0" (setting that uses PLL clock.)
In addition, this reset does not change the CRG module register, VINITHI control register of
remap/boot controller (RBC) or the INITRAM control register.
The clock source of the software reset is time based on the timer's count value. It is cleared
when a software reset is asserted.
This software reset generates the internal signal, which does not reset as CRSTn.
3. XSRST (reset request from a debugging tool)
This signal is a reset request from a debugging tool (e.g. MultiICE) and an internal reset
request can be transmitted by the tool through the XSRST pin. This module recognizes the
reset signal as the same reset request as that of an external reset.
4. XTRST (built-in ICE macro reset request from a debugging tool)
This signal is a built-in ICE macro reset request from a debugging tool (e.g. MultiICE) and
the reset signal requests a reset from the embedded ICE macro in the ARM9 core.
Although the reset signal is asserted, other peripherals are not initialized. The embedded
ETM9CS Single trace cell is also reset by this signal.
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