MB86R02 'Jade-D' Hardware Manual V1.64
23 Run-Length Decompression (RLD)
23.1 Position of Block in whole LSI
Figure 23-1 Location of the RLD unit in the GDC
23.1.1
Data Flow in the LSI
MEMC
CCPB
S
Data input flow
Phase 1
HDMAC initiates a transfer form CCBP to RLD. Data will be latched into HDMAC's FIFO
Phase2
HDMAC prompts FIFO data to input FIFO of RLD
Phase3
RLD decompresses the FIFO data and transfers them to Target destination
HDMAC
SRAM
8ch
32KB
S
M
S
AHB
S
RLD
Figure 23-2 Example position in LSI
SRAM
MLB
32KB
S
M
S
M
Data output flow
AHB2AXI
S
23-1