Medialb Signal Timing; Medialb Ac Spec Type A - Fujitsu MB86R02 Jade-D Hardware Manual

Graphics controller

Hide thumbs Also See for MB86R02 Jade-D:

Table of Contents

MB86R02 'Jade-D' Hardware Manual V1.64

MediaLB Signal Timing

Ground = 0V; Load capacitance = 60pF; MediaLB speed = 256Fs or 512Fs; Fs = 48kHz; all timing

parameters specified from the valid voltage threshold as listed below; unless otherwise noted.

Table 34-36 AC Timing of Clock Signal

*1: The controller can shut off MLBCLK to place MediaLB in a low-power state.

*2: Pulse width variation is measured at 1.25V by triggering on one edge of MLBCLK and measuring the

spread on the other edge, measured in ns peak-to-peak (pp).

Input Signal

Table 34-37 AC Timing of Input Signal

MLBSIG, MLBDAT

Output Signal

Table 34-38 AC Timing of Output Signal

MLBSIG, MLBDAT

MLBCLK operating

frequency (*1)

MLBCLK rising time

MLBCLK falling time

MLBCLK cycle time

MLBCLK low time

MLBCLK high time

MLBCLK pulse width

MLBSIG and MLBDAT input

valid to MLBCLK falling

MLBSIG and MLBDAT input

hold from MLBCLK low

MLBSIG and MLBDAT output

high impedance from MLBCLK

Bus hold time