Interrupt; Ahb Slave Module Access Error Response; Reset Request - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
16.3.3.

Interrupt

16.3.3.1.

AHB slave module access error response

An error response from the AHB bus is output to the chip control module, CCNT. In addition, an
error response is written to the STATUS byte and the host CPU is immediately notified. The
RxRDY bit (or TxRDY bit) is set to '1' at the same time. The HOSTIF module itself does not have
a register to maintain this information.
Host CPU
HOST DO
Rx
RDY
(wri te a cces s ) "0"
(rea d a cces s ) "1"
HOST INT
Initial:Disable
When an error response status has been sent to the host CPU, the transaction is completed. If
the CCNT interrupt setting is enabled, an interrupt is generated.
16.3.4.

Reset Request

A software reset of MB86R02 can be executed on request by the host CPU. If the normal
operation of the MB86R02 device is no longer possible due to certain conditions, the host CPU
can use the reset request. When a reset is executed, the MB86R02 is rebooted by the CRG unit.
Host CPU
HOST DI
16-6
from
AHB bus
HOST-IF
CNT
Tx
1 1 1 1 1
SERR
RDY
"1" "1"
Status byte
"0" "1"
Figure 16-6 Interrupt
HOST-IF
CNT
CMD byte
ABL1 ABL0 DBL2 DBL1 DBL0 R/W CNT1 CNT0
"1" "0"
Figure 16-7 Reset request
o_HST_INT
interrupt
CCNT
Reset req ox_HST_ASRST
ix_HRESET
CCNT
from
internal
module
INT
status
Reg
All_soft
_Reset
CRG