Dma Configuration Register (Dmacr) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

15.6.2 DMA configuration register (DMACR)

Address
Bit 31 30 29
Name DE DS
R/W R/W R R
Initial value 0 0 0
Bit 15 14 13
Name
R/W R R R
Initial value 0 0 0
Bit field
No. Name
31 DE Transfer is controlled for all DMA channels.
(DMA
Enable)
0
1
[Transfer gap]
The transfer gap is that DMAC de-asserts bus request (HBUSREQ) to the arbiter during DMA
transfer (about 4 clocks) by DMAC. Its occurrence is different by transfer mode shown
below.
•
•
•
This bit can be used to reset all channels of Configuration register at a time during DMA
transfer.
30 DS This shows all channels of DMA transfer is stop.
(DMA Stop)
0
1
This bit is set to "1" during DMA transfer by either of following operations:
•
•
When the state of disable/halt is cleared, DMAC clears DS bit to "0".
This bit is able to use for confirmation of transfer stop when DMAC stops transfer of all
channels by disable/halt setting.
29 (Reserved) Reserved bits. Write access is ignored.
Read value of this bit is always "0".
28 PR Prioritization procedure of DMA channel is controlled.
(Priority
Rotation)
0
1
Channel switch occurs by the timing of transfer gap.
Refer to DE bit description for the transfer gap.
15-6
28 27 26 25
- PR DH[3:0]
R/W R/W R/W R/W R/W
0 0 0 0
12 11 10 9
R R R R
0 0 0 0
All DMA channels are disabled and DMA transfer is not performed until "1" is
set to this bit
If the value is cleared to "0" during the transfer, DMA is stopped at transmission
gap for the channel in transfer
DMA transfer starts according to the register setting of each channel
Block transfer: Transfer gap occurs at BC = 0 (after completing transfer in BC unit)
Burst transfer: There is no transfer gap.
Demand transfer: Transfer gap occurs at TC = TC - 1 (after completing 1 DMA
transfer), or at transfer request negotiation
Release of disable/halt setting
DMA transfer stop of all channels by disable/halt setting
DMACR.DE bit is cleared to "0" (all channels are disabled)
Value other than 4'h0 is set to DMACR.DH bit (all channels are halt)
"Fixed"
Priority order: Ch0 > Ch1 > Ch2 > Ch3 > Ch4 > Ch5 > Ch6 > Ch7
"Rotation"
Priority order is rotated
FFFD_0000 + 00(h)
24 23 22 21
R R R
0 0 0 0
8 7 6 5
(Reserved)
R R R R
0 0 0 0
Description
20 19 18 17
(Reserved)
R R R R
0 0 0 0
4 3 2 1
R R R R
0 0 0 0
16
R
0
0
R
0