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MB86R02 'Jade-D' Hardware Manual V1.64
23.6.4
Register Description
SWReset
Register address
BaseAddress + 0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field name
R/W
Reset value
SW reset
Bit 0
SWReset
sw reset (flush all FIFOs)
RldCfg
Register address
BaseAddress + 4
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Field name
R/W
Reset value
general configuration register
Bit 8
AlignMode
output data format 0b=bit alligned output 1b=word (32bit) alligned output
Bit 2 - 0
BPP
Bit per pixel, 000b=1, 001b=2, 010b=4, 011b=8, 100b=16, 101b=24, 110b=32 others=reserved
StrideCfg0
Register address
BaseAddress + 8
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field name
R/W
Reset value
Stride general configuration register
Bit 0
StrideEn
Enable for output data stride alligned, 0b=disabled (no observation of LineLength and Stride, needed for 4x4 1bpp sprites),
1b=enabled
StrideCfg1
Register address
BaseAddress + C
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field name
R/W
Reset value
Line / Stride Length
Bit 31 - 16
Stride
Stride: number of byte -1 (must to be 4byte aligned)
Bit 13 - 0
LineLength
number of bytes per line - 1 (must to be 4byte aligned)
BYTECNT
Register address
BaseAddress + 10
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field name
R/W
Reset value
Target number of decompressed bytes
Bit 31 - 0
ByteCnt
Target number of decompressed bytes
23-6
H
H
H
H
Stride
RW
0
H
H
ByteCnt
RW
0
H
SWReset
RW
0
H
8
7 6 5 4 3 2 1 0
AlignMode
BPP
RW
RW
0
0
H
H
StrideEn
RW
0
H
LineLength
RW
0
H
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