Fujitsu MB86R02 Jade-D Hardware Manual page 285

MB86R02 'Jade-D' Hardware Manual V1.64
Restrictions
When DMA transfer is performed by external (DREQ) and peripheral (IDREQ) requests, there
are some restrictions for external and peripheral signal pins.
1. DREQ/IDREQ
DREQ/IDREQ must be asserted for at least 2 cycles of the AHB clock (HCLK).
There is no restriction for the timing of the negation of DREQ/IDREQ.
After completing DMA transfer in BC × TC and asserting DACK/IDACK and DEOP/IDEOP, a
new transfer request (edge of DREQ/IDREQ) can be accepted for the next DMA transfer.
2. DACK/IDACK
After the DMAC has transferred data to the destination address, DACK/IDACK are asserted
for 1 cycle of the AHB clock (HCLK). If access to the destination was done correctly, this
signal is asserted.
If the destination issues error, retry, or split responses on the AHB bus, this signal is not
asserted.
In burst transfer mode, these signals indicate that the DMAC has performed destination
access properly.
3. DEOP/IDEOP
Basically, DEOP/IDEOP are asserted for 1 AHB clock (HCLK) cycle when the DMAC ends
DMA transfer properly or abnormally. Abnormal DMA transfer includes the following cases:
• Forced termination by DSTP/IDSTP
• Forced termination by setting 1'b0 to DMACA/EB
• Reception of an error response from the source/destination
4. DSTP/IDSTP
DSTP/IDSTP are used to forcibly terminate DMA transfer and it is permissible to assert them
during transfer (it is also permissible to assert DSTP/IDSTP while DMA is not transferring
due to the transfer gap or an interrupt function).
If these signals are used to forcibly terminate DMA transfer, they are not asserted until
DEOP/IDEOP are asserted.
5. Exceptional operation of DEOP/IDEOP
If DSTP/IDSTP are asserted immediately after DREQ/DSTP have been asserted, the DMAC
may request the bus to execute an IDLE transfer. In this case, the DMAC may assert
DEOP/IDEOP for 2 cycles or more of the AHB clock (HCLK).
The assertion period of DEOP/IDEOP depends on the number of previous master transfer
cycles. Figure 15-4 shows an example of this exception operation.
15-22