Fujitsu MB86R02 Jade-D Hardware Manual page 102

MB86R02 'Jade-D' Hardware Manual V1.64
Bit field
No. Name
2 WDTSET
/WDTCLR
1-0 WDTMODE[1:0] These bits set timing to clear watchdog timer.
5-22
Setting and clear of watchdog timer
This bit sets and clears watchdog timer which starts count at writing "1" and clears at
writing "1" from the second time.
0 The watchdog timer is not set (Initial value)
First time:
1
Second time or later: The watchdog timer is cleared
Writing 0 is ignored.
Watchdog reset occurs at following period when "1" is written to WDTSET/WDTCLR
bits at the end.
× 2 n0 × 2
00 T ~ T
CLK CLK
× 2 n1 × 2
01 T ~ T
CLK CLK
× 2 n2 × 2
10 T
~ T
CLK CLK
× 2 × 2
n3
11 T
~ T
CLK CLK
T : Cycle time of external pin CLK
CLK
n0 = 9
n1 = 12
n2 = 14
n3 = 16
Select the bit that is corresponded to the system.
Description
The watchdog timer starts
(n0 + 1)
(initial value)
(n1 + 1)
(n2 + 1)
(n3 + 1)