Multiple Interrupt Processing; Example Of Irq Interrupt Handler - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

9.6.3 Multiple interrupt processing

The example of executing the multiple interrupt processing is shown.
Main routine
CPSR→SPSR_irq
IRQ request 1→

9.6.4 Example of IRQ interrupt handler

IRQ_Handler ROUT
STMFD SP!, {R0-R12, R14}
MESSAGE "Enter Dummy IRQ Handler"
LDR R0, = ILM
LDR R1, [R0]
MRS R2, SPSR
STMFD SP!, {R1, R2}
LDR R2, = ICRMN
LDR R1, [R2]
STR R1, [R0]
9-28
The first interrupt process
(1) Save the register value in the stack.
(2) Save a present ILM register value and SPSR_irq
(existence in the core) register value in the stack.
Do not lose by the following interrupt process.
(3) Set the value of the ICRMN register to the ILM register,
and interrupt effectively at a level that is higher than the
first interruption.
(4) The interruption source that is occurring currently is clear.
(5) The IRQF flag is clear (NIRQ is negated, and the decision
of the interruption level restarts).
(6) Confirm the clearness of the IRQ flag.
(7) Clear I bit to the CPSR register in the ARM7TDMI core
and enable the interruption reception.
IRQ request 2→
The first interrupt return process
Do the same interrupt return process
as the second to the first interruption.
Figure 9-3 Multiple IRQ interrupt processing example
;The register value is preserved.
;Preserve the value of ILM and the SPSR_irq register.
;Set the ICRMN register value to the ILM register.
The second interruption process
Do the same interrupt process as
the first to the second interruption.
The second interruption return process
(1) Set I bit of the CPSR register, and
disable the interruption.
(2) Restore the value of SPSR_irq saved
in the stack to the SPSR_irq register.
(3) Restore the value in the stack to the
register.
(4) Restore the PC value to return to former
routine, and restore the
register value to the CPSR register.
SPSR_irq