Dram Control Mode Register (Drcm) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

13.6.6 DRAM control mode register (DRCM)

This register sets operation mode of DRAM, and the same setting as DRAM should be set. The
operation mode is unable to be changed due to DDRIF macro and other restrictions.
Address
Bit 15 14 13
Name - - -
R/W R/W R/W R/W
Initial value X X X
Bit field
No. Name
15-13 (Reserved)
12 BT
11 (Reserved)
10-8 AL
7 (Reserved)
6-4 CL
3 (Reserved)
2-0 BL
Note:
• The DRCM register is unable to be used for DRAM initialization.
• Set operation mode of DRAM control core at normal operation to this register. When
DRINI bit (bit 15) of DRAM initialization control register becomes "0" (normal operation
mode), DRAM control core operates according to the DRCM register setting. Be sure
to complete the setting before "0" is set to the DRINI bit.
12 11 10 9
BT - AL
R R/W R
0 X 0 0
Reserved bits.
Write access is ignored.
Only sequential is applied in the burst type setting.
Setting to DRAM should also be "sequential".
0 Sequential (initial value)
1 Reserved (setting prohibited)
Reserved bit.
Write access is ignored.
Additive latency is set.
This module operates with AL = 0, and it should also be set to DRAM.
Reserved bit.
Write access is ignored.
CAS latency is specified.
011 CL = 3 (fixed)
Others Reserved (setting prohibited)
DRAM setting should also have the same as this register's.
Reserved bit.
Write access is ignored.
Burst length is specified.
010 BL = 4 (fixed)
Others Reserved (setting prohibited)
DRAM setting should also have the same as this register's.
F300_0000 + 08
H H
8 7 6 5
- CL
R/W R/W
0 X 0 1
Description
4 3 2 1
- BL
R/W R/W
1 X 0 1
13-9
0
0