Operation; Dram Initialization Sequence - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

13.7 Operation

This section describes DDR2C operation.

13.7.1 DRAM Initialization Sequence

Initialization sequence at using DDR2SDRAM is described below.
Figure 13-2 shows initialization sequence at using DDR2SDRAM in time chart.
To proceed memory access to DDR2SDRAM, initialization sequence should be performed after
power-on.
During initialization sequence, DDRIF macro setting, DLL reset release in DDRIF macro, SDRAM
initialization, OCD adjustment, ODT setting, and others are processed. Refer to "13.7.2
DRAM Initialization Procedure" for more detail of initialization sequence.
Power-on
XRST
(CHIP RESET)
IRESET*5
(DDRIF Macro RESET)
IUSRRST*5
(DDRIF Macro RESET)
IDLLRST*5
(DDRIF Macro DLL RESET)
MCKP
(DDR2 IF CLK)
MCS
(DDR2 IF XCS)
MCKE
(DDR2 IF CKE)
ODTCONT
(DDR2 IF ODT)
(2) DDRIF macro register
(3) 120[ns] or more*2
(1) *1
(4) IRESET/IUSRRST release
(5) 120[ns] or more*2
*1 PLL lock up time or more
*2 MCKP cycle (166MHz=6[ns]) × 20cycle = 120[ns]
*3 DLL lock up time or more (79[us])
*4 Based on DDR2SDRAM spec
*5 This is internal signal of CHIP, not pin signal (DDRIFmacro module input signal)
Figure 13-2 DDR2SDRAM initialization time chart
(10) SDRAM
initialization
(6) IDLLRST release
(7)79[us] or more *3
(8)200[us] or more *4
(9) MCKE on
(11) OCD adjustment,
ODT setting (CHIP
side)
(12) ODTCONT-on
Shifting to DDR2C
normal operation mode
13-27