Block Diagram - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

13.4 Block Diagram

Figure 13-1 shows block diagram of DDR2 controller (DDR2C.)
Write address channel
Write data channel
Write response channel
AXI IF
Read address channel
Read data channel
AHB IF
83MHz
operation
AXI RESET
AHB RESET
Block
•
AHB IF
•
•
AXI IF
•
•
•
FIFO
•
•
•
DRAM IF
•
•
DDRIF macro
•
•
•
SSTL_18 I/O
•
13-2
write Data
AXI IF
with
arbiter
Read control
Read data
Control signal
AHB IF
( Register)
166MHz
operation
Figure 13-1 Block diagram of DDR2 controller (DDR2C)
Slave function of AHB IF
Control register.
Slave function of AXI IF
FIFO control function
Address/Write
Data/Read
Control/Read
Data storage FIFO
DDRIF macro control function
SDRAM IF control function
Connection between DRAM IF module and IO (Read data's importing phase
adjustment)
Built-in DLL
STUB series terminated logic for 1.8V single end buffer (OCD and ODT functions
are embedded)
STUB series terminated logic for 1.8V differential buffer (OCD and ODT functions
are embedded)
ODT auto. adjustment function
Table 13-1 Individual block function
FIFO
address
Add
WData
FIFO
DRAM IF
RData
FIFO
FIFO
Function
DDR2SDRAM
SSTL_18
DDRIF
IF
I/O
Macro
VREF0/1
OCD/ODT
ODTCONT