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MB86R02 'Jade-D' Hardware Manual V1.64
11.6 Register
This section describes 32 bit width external bus I/F register.
Be sure to access to it in word (32 bit.)
11.6.1 SRAM/Flash mode register 0/2/4 (MCFMODE0/2/4)
Register address
Bit No.
31
Bit field name
R/W
Initial value
Bit No.
15
Bit field name
R/W
Initial value
Bit31-7: Reserved
Reserved bits.
Write "0" to these bits. Their read value is undefined.
Bit6: RDY (ready mode)
When handshake is performed with low-speed peripherals that use MEM_RDY signal,
set this bit to "1". RDY signal at reading should be asserted to "L" at least 2 cycles
from 2 cycles before falling edge of MEM_XRD signal to actual falling edge. For the
writing operation, the RDY signal should also be asserted to "L" at least 2 cycles from
2 cycles before falling edge of MEM_XWR signal to actual falling edge.
For accessing to device such as SRAM memory without using the MEM_RDY signal,
this bit should be set to "0".
0:
1:
Bit5: PAGE (page access mode) NOR flash page access mode
This bit controls NOR flash page access mode which issues the first address cycle
according to FirstReadAddressCycle (FRADC) setting. Then, the access is
continuously executed according to Read Access Cycle (RACC) setting until it reaches
to 16 byte boundary. In order to select this mode, set Read Address Cycle (RADC) to
0.
0:
1:
Bit4-2: Reserved
Reserved bits.
Write "0" to these bits. Their read value is undefined.
Note:
Writing "1" to these bits are prohibited.
BaseAddress+0x0000(MEM_XCS[0]),
BaseAddress+0x0008(MEM_XCS [2]),
BaseAddress+0x0010(MEM_XCS [4])
30
29
28
27
26
14
13
12
11
10
Reserved
R/W0
X
READY mode OFF (initial value)
READY mode ON
NOR flash page access mode OFF (initial value)
NOR flash page access mode ON
25
24
23
22
21
Reserved
R/W0
X
9
8
7
6
5
PAG
RDY
E
R/W R/W
0
0
20
19
18
17
16
4
3
2
1
0
Reserved
WDTH
R/W0
R/W
X
X
X
0 *1
11-3
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