Fujitsu MB86R02 Jade-D Hardware Manual page 747

MB86R02 'Jade-D' Hardware Manual V1.64
Bit field
No. Name
19 EOPI This is interrupt flag containing reception timer. The timer is enabled when following
conditions are met at the same time:
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•
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After the reset, operation starts with the 1st word reception. Then the value is cleared
every time word is received. When reception FIFO is not empty at the time set to RPTMR
of INTCNT register, the value is set to "1". When EOPI is "1" and EOPM of INTCNT
register is "0", interrupt to CPU occurs. The value is automatically cleared if reception
FIFO data is threshold or more, or it becomes empty.
Writing "1" from CPU clears the value to "0".
This becomes "0" by software reset.
18 BSY Serial transmission control part is busy state. This bit is not affected by software reset.
17 TXFI When empty slot of transmission FIFO is larger than the threshold set in TFTH of INTCNT
register, this bit is set to "1".
This bit is "1" and TXFIM bit of INTCNT register is "0": Interrupt to CPU occurs
This bit is "1" and TXFDM bit of INTCNT register is "0": DMA is requested
When number of empty slot of reception FIFO becomes smaller than the threshold by
writing to TXFDAT register from CPU or DMAC, this bit is cleared automatically to "0".
The value is also become "0" when start bit of start register is "0" and TXENB bit of
OPRREG register is "0". If software reset is performed at start bit = "1" and TXENB bit =
"1", the value becomes "0" during software reset then changes to "1" after the process.
16 RXFI When number of reception FIFO data is larger than the threshold set in RFTF of INTCNT
register, this bit is set to "1".
This bit is "1" and RXFIM bit of INTCNT register is "0": Interrupt to CPU occurs
This bit is "1" and RXFDM bit of INTCNT register is "0": DMA is requested
When number of data in reception FIFO becomes smaller than the threshold by reading
RXFDAT register from CPU or DMAC, this bit is automatically cleared to "0".
When start bit of start register is "0" or RXENB bit of OPRREG register is "0", this bit
becomes "0".
This becomes "0" by software reset.
15-14 (Reserved) Reserved bits.
The write access is ignored. The read value of these bits is always "0".
13-8 TXNUM[5:0] The number of data in transmission FIFO is indicated.
This bit is incremented by write access to TXFDAT register and decremented by serial word
transfer.
Max. value of 66 can be displayed in the simultaneous transfer mode, and value of 132 in
the transmission only mode.
This becomes "0" by software reset.
7-6 (Reserved) Reserved bits.
The write access is ignored. The read value of these bits is always "0".
5-0 RXNUM[5:0] The number of data in reception FIFO is indicated.
This bit is incremented by word reception from serial bus and decremented by read access
to RXFDAT register.
Max. values of 66 can be displayed in the simultaneous transfer mode, and value of 132 in
the reception mode.
This becomes "0" by software reset.
27-20
RXDIS of CNTREG register is set to "0"
RXFDM of INTCNT register is set to "0"
MSMD of CNTREG register is set to "0"
start bit of OPRREG register is set to "1" and RXENB = "1"
0 Serial transmission control part is in idle
1 Serial transmission control part is in busy
Description