I2Sxtxfdat Register - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

27.6.4 I2SxTXFDAT register

This register is transmission FIFO register that is able to maintain up to 66 words (simultaneous
transfer mode) or 132 words (transmission only mode.)
Address
Bit 31 30 29
Name
R/W W W W
Initial 0 0 0
Bit 15 14 13
Name
R/W W W W
Initial 0 0 0
Bit field
No. Name
31-0 TXDATA[31:0] Word to be transmitted is able to be written as long as transmission FIFO is not full.
ch0：FFEE_0004 (h)
28 27 26 25
W W W W
0 0 0 0
12 11 10 9
W W W W
0 0 0 0
Write access is able to be performed regardless of shift register's operation status.
The word written to full transmission FIFO is actually not written. Although writing data
is accessed in word, half-word, and byte access, actual number of bit to be transmitted
is determined by S0WDL and S1WDL (when frame is 2 sub frame) of MCR0REG
register.
The data read from TXDATA is invalid one (the data after right justified last written data.)
24 23 22 21
TXDATA
W W W W
0 0 0 0
8 7 6 5
TXDATA
W W W W
0 0 0 0
Description
20 19 18 17
W W W W
0 0 0 0
4 3 2 1
W W W W
0 0 0 0
27-7
16
W
0
0
W
0