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MB86R02 'Jade-D' Hardware Manual V1.64
Bit
init
Name
ial
cfg_trigger_active_length[6]
7
0
cfg_trigger_active_length[5]
6
0
cfg_trigger_active_length[4]
5
0
cfg_trigger_active_length[3]
4
0
cfg_trigger_active_length[2]
3
0
cfg_trigger_active_length[1]
2
0
cfg_trigger_active_length[0]
1
1
reserved
0
0
Table 17-4 TX config_byte_9
Bit
init
Name
ial
cfg_trigger_offset[6]
7
0
cfg_trigger_offset[5]
6
0
cfg_trigger_offset[4]
5
0
cfg_trigger_offset[3]
4
0
cfg_trigger_offset[2]
3
0
cfg_trigger_offset[1]
2
0
cfg_trigger_offset[0]
1
1
reserved
0
0
Table 17-5 TX config_byte_10
17-32
config_byte_9
Description
APIX PHY (Soft IP): configures high pulse
width of signal 'sbdown_trigger' (multiples
of core clk cycle)
0: 1 cycle
1: 2 cycles (default)
2: 3 cycles
...
71: 72 cycles
do not change
config_byte_10
Description
APIX PHY (Soft IP): configure start position
of signal 'sbdown_trigger' (multiples of core
clk cycle relative to "strobe position")
0: 0 cycles ("strobe")
1: 1 cycle ("request")
1: 2 cycles
...
71: 71 cycles
do not change
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