Fujitsu MB86R02 Jade-D Hardware Manual page 272

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MB86R02 'Jade-D' Hardware Manual V1.64
Bit field
No.
Name
29
ST
This bit is used to generate software trigger.
(Software
Trigger)
When "1" is set to this bit, DMA transfer starts as software request is received. After the
transfer, DMAC sets "0" to this bit.
If "0" is set to this bit during DMA transfer by software request, it stops at transfer gap.
28-24
IS[4:0]
This bit is used to select trigger for DMA transfer.
(Input Select)
DMA transfer trigger is software request (ST = 1):
DMA transfer trigger is external request (DREQ):
DMA transfer trigger is peripheral request (IDREQ[15:0]):
External request (DREQ[7:0]) is allocated into each corresponding channel (e.g.
DREQ[0] corresponds to DMA Channel 0, DREQ[1] to DMA Channel 1, and so on) and
peripheral request (IDREQ[15:0]) is allocated into all channels. Thus, peripheral request
can be selected from all channels.
Transfer mode is block transfer or burst transfer: Rising edge is selected.
Transfer mode is demand transfer: "H" active level is selected.
[Note]
0
Initial value
1
Software request
IS[4:0]
0(h)
Software request
1(h)-B(h)
Invalid
E(h)
DREQ "H" active level or rising edge
F(h)
DREQ "L" active level or falling edge
10(h)
IDREQ 0 "H" active level or rising edge
11(h)
IDREQ 1 "H" active level or rising edge
12(h)
IDREQ 2 "H" active level or rising edge
13(h)
IDREQ 3 "H" active level or rising edge
14(h)
IDREQ 4 "H" active level or rising edge
15(h)
IDREQ 5 "H" active level or rising edge
16(h)
IDREQ 6 "H" active level or rising edge
17(h)
IDREQ 7 "H" active level or rising edge
18(h)
IDREQ 8 "H" active level or rising edge
19(h)
IDREQ 9 "H" active level or rising edge
1A(h)
IDREQ 10 "H" active level or rising edge
1B(h)
IDREQ 11 "H" active level or rising edge
1C(h)
IDREQ 12 "H" active level or rising edge
1D(h)
IDREQ 13 "H" active level or rising edge
1E(h)
IDREQ 14 "H" active level or rising edge
1F(h)
IDREQ 15 "H" active level or rising edge
These bits must not be the same as other channels
If these bits are changed at asserting DREQ/IDREQ, DMAC regards IS bit change as
edge (rising edge/falling edge) detection.
Description
Set 5'b00000 to IS bit
Set 5'b01110 or 5'b01111 to IS bit
Set 5'b1xxxx to IS bit
Function
15-9

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