Clock Divider Control Register B (Crdb) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
5.1.6.

Clock divider control register B (CRDB)

This register controls clock divider.
Address
Bit 31 30 29
Name – – –
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value X X X
Bit 15 14 13
Name
R/W R0 R0 R0
Initial value 0 0 0
Bit field
No. Name
31-16 –
15-3 (Reserved)
2-0 HBDM[2:0]
28 27 26 25
– – – –
X X X X
12 11 10 9
(Reserved)
R0 R0 R0 R0
0 0 0 0
Unused bits.
Write access is ignored, and read value of these bits is undefined.
Reserved bits.
Write access is ignored, and read value of these bits is always "0".
HBCLK frequency dividing mode
These bits set frequency dividing ratio of HBCLK.
HBDM[2:0] Frequency dividing ratio of HBCLK
000
f = f
HBCLK CCLK
001
f = f
HBCLK CCLK
010 f = f
HBCLK CCLK
011 f = f
HBCLK CCLK
100 f = f
HBCLK CCLK
Others Reserved (setting prohibited)
f : Clock frequency of HBCLK
HBCLK
f : Clock frequency of CCLK
CCLK
FFFE_7000 + 14
H H
24 23 22 21
– – – –
X X X X
8 7 6 5
R0 R0 R0 R0
0 0 0 0
Description
× (1/1)
× (1/2) (initial value)
× (1/4)
× (1/8)
× (1/16)
20 19 18 17
– – – –
X X X X
4 3 2 1
HBDM[2:0]
R0 R0 R/W R/W R/W
0 0 0 0
5-27
16
–
X
0
1