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MB86R02 'Jade-D' Hardware Manual V1.64
OFIFO
Register address
BaseAddress + 14
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field name
R/W
Reset value
Output FIFO Control
Bit 3 - 0
WriteThreshold
number of words-1 after which a write burst is initialized
DestAddress
Register address
BaseAddress + 18
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4
Field name
R/W
Reset value
Local AHB-master transfer Destination address (byte address)
Bit 31 - 2
AHBMDA
Destination address to start AHB-master transfer (word address)
Bit 1 - 0
Reserved, do not change, only value 00 is supported!
AHBMCtrl
Register address
BaseAddress + 1C
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
Field name
R/W
Reset value
Local AHB-master transfer Configuration/Control
Bit 23 - 16
Reserved0
Bit 9 - 8
AHBMTransferWidth
00b=byte, 01b=halfword, 10b=word, 11b=reserved
Bit 0
AHBMFixedDest
0b=destination address is incremented, 1b=destination address is fixed
RLDCtrl
Register address
BaseAddress + 20
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3
Field name
R/W
Reset value
General Control
Bit 0
AcceptData
Enable Acceptance of compressed Data, reseted by HW after completion
IEN
Register address BaseAddress + 24
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
Field name
R/W
Reset value
Interrupt Enable register
Bit 3
IEnIFfull
Interrupt enable
Bit 2
IEnIFempty
Interrupt enable
Bit 1
IEnError
Interrupt enable
Bit 0
IEnComplete
Interrupt enable
ISTS
Register address BaseAddress + 28
H
H
AHBMDA
RW
H
Reserved0
RWS
0
H
H
H
H
0
H
11
10
AHBMTransferWidth
RW
0
H
7
6
IEnIFfull IEnIFempty IEnError IEnComplete
RW
0
H
WriteThreshold
RW
0
H
3
2 1 0
reserved
RW
0
H
9
8 7 6 5 4
3
2
1
0
AHBMFixedDest
RW
0
H
2 1 0
AcceptData
RW
0
H
5
4
3
2
1
0
RW
RW
RW
0
0
0
H
H
H
23-7
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