Divider Latch Register (Urtxdll&Urtxdlm) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
28.6.11 Divider latch register (URTxDLL&URTxDLM)
This register is frequency dividing latch to generate necessary baud rate from clock input.
Frequency diving latch consists of 16 bit, DLM (high order byte) and DLL (low order byte.)
[DLL]
ch0：FFFE_1000 + 00h ch1：FFFE_2000 + 00h ch2：FFF5_0000 + 00h
Address
ch3：FFF5_1000 + 00h ch4：FFF4_3000 + 00h ch5：FFF4_4000 + 00h
Bit 31 30 29
Name
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value X X X
Bit 15 14 13
Name
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
valu X X X
e
[DLM]
ch0：FFFE_1000 + 04h ch1：FFFE_2000 + 04h ch2：FFF5_0000 + 04h
Address
ch3：FFF5_1000 + 04h ch4：FFF4_3000 + 04h ch5：FFF4_4000 + 04h
Bit 31 30 29
Name
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value X X X
Bit 15 14 13
Name
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
valu X X X
e
DLL and DLM are read/written when DLAB bit of LCR is set to "1".
• After the reset, DLL and DLM are 00h
• DLL and DLM values are loaded by writing to either DLL or DLM
• Baud rate is settable in the range that DLM and DLL are FFFFh ~ 0001h
28-14
(Accessing is enabled only at DLAB = 1)
28 27 26 25
X X X X
12 11 10 9
(Reserved)
X X X X
(Accessing is enabled only at DLAB = 1))
28 27 26 25
X X X X
12 11 10 9
(Reserved)
X X X X
24 23 22 21
(Reserved)
X X X X
8 7 6 5
X 0 0 0
24 23 22 21
(Reserved)
X X X X
8 7 6 5
X 0 0 0
20 19 18 17
X X X X
4 3 2 1
DL[7:0]
0 0 0 0
20 19 18 17
X X X X
4 3 2 1
DL[15:0]
0 0 0 0
16
X
0
0
16
X
0
0