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MB86R02 'Jade-D' Hardware Manual V1.64
Register
BaseAddress + 20
H
address
Bit
31
30 29 28 27 26 25 24 23 22 21 20 19 18 17
number
Field
SSCG_PD
name
R/W
RW
Reset
1
H
value
SSCG control register
Bit 31
SSCG_PD
Power down for internal SSCG analog units (1=power down, 0=active)
Bit 16
SSCG_BYPASS
0: Use SSCG modulation, 1=BYPASS (no SSCG modulation)
Bit 8
SSCG_PEAK_FREQUENCY
0: Normal operation , 1: SSCG test operation
Bit 6
SSCG_FREQ
- 4
000: input frequency in range of 400MHz and 550 MHz, 001: input frequency in range of 550MHz and 700 MHz, 010: input frequency in range of
1.0GHz and 1.3 GHz, 011: input frequency in range of 1.3GHz and 1.6 GHz
Bit 1
SSCG_TYPE
- 0
00= none, 01=down spread, 10=up spread, 11=centre spread
SSCG_ENABLE
Register address
BaseAddress + 24
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Field name
R/W
Reset value
SSCG Start/Stop control register
Bit
SSCG_EN
0
0=Follow PLL frequency +/- SSCG_FOFFSET , NON-SSCG You can modify the configuration register. SSCG processing can be continued by
setting SSCG_EN=1, 1=Enable SSCG spread spectrum unit. if enabled, you are NOT allowed to modify any configuration registers except
SSCG_ENABLE and SSCG_FREQUENCY_MEASUREMENT.
SSCG_FREQUENCY_MEASUREMENT
Register address
BaseAddress + 2C
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field name
R/W
Reset value
Measurement position and measurement duration
Bit 27 -
SSCG_CNTLEN
16
Measure output frequency over n PLL clocks * 256 after CNTSTART (1lsb=256 PLL clocks, requirement: (SSCG_CNTSTART +
SSCG_CNTLEN) less then 95% of SSCG_PERIOD)
Bit 11 -
SSCG_CNTSTART
0
Delay from the start of the modulation period to the start of the measurement in PLL clocks * 256 (1lsb=256 pll-clocks)
SSCG_COUNT_TYPE
Register
BaseAddress + 30
H
address
Bit
31
number
Field
SSCG_MEASURE_CLK_DEAD
name
R/W
RW
Reset
0
H
value
Measurement type
Bit 31
SSCG_MEASURE_CLK_DEAD
SSCG_MEASURE_CLK_DEAD: 0 = deactivate clock_dead measure function, 1 = activate clock_dead measure function (CNTOUTFREQ = 0 if
no modulated clock)
Bit 18 -
SSCG_CNT_MULTIPLE
16
(Jade_D Plus version only) CNT_MULTIPLE: 0: measurement of 1 period, 1: 2 periods, 2: 4 periods, 3: 8 periods, 4: 16 periods, 5: 32 periods, 6:
64 periods, 7: 128 periods
Bit 8
SSCG_CNT_AVERAGE
6-6
16
SSCG_BYPASS
RW
1
H
H
H
SSCG_CNTLEN
RW
25
H
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
15 14 13 12 11 10 9
8
SSCG_PEAK_FREQUENCY SSCG_FREQ
RW
0
H
SSCG_CNT_AVERAGE
RW
0
H
7 6
5
4 3 2
1
SSCG_TYPE
RW
1
H
0
SSCG_EN
RW
0
H
SSCG_CNTSTART
RW
0
H
8
7 6 5 4 3 2 1
SSCG_CNTREPEAT
RW
0
H
0
RW
3
H
0
RW
0
H
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