Uart Signal Timing - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
34.5.10

UART Signal Timing

Table 34-32 AC Timing
Signal Symbol
UART_SOUT0
UART_SOUT1
UART_SOUT2
t
do
UART_SOUT3
UART_SOUT4
UART_SOUT5
UART_SIN0
UART_SIN1
UART_SIN2
t
dw
UART_SIN3
UART_SIN4
UART_SIN5
t
UART_XRTS0
rtso
t
UART_XCTS0
ctsw
Internal clock is the standard of output delay.
A indicates APB bus clock cycle, and it is different from the output delay standard clock.
Internal CLK
UART_SOUT0
UART_SOUT1
UART_SOUT2
UART_SOUT3
UART_SOUT4
UART_SOUT5
UART_XRTS0
UART_SIN0
UART_SIN1
UART_SIN2
UART_SIN3
UART_SIN4
UART_SIN5
UART_XCTS0
Figure 34-32 UART Timing
Description
Data output delay time
Input data width
XRTS output delay time
Input XCTS data width
t
do
t
rtso
Min.
–
16A
–
A
t
dw
～ ～
t
ctsw
～ ～
Value
Unit
Typ. Max.
– 12 ns
– – ns
– 11 ns
– – ns
34-37