Demand Transfer - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
15.7.1.4

Demand transfer

Operation
In demand transfer mode, DMA transfer is executed as a one-off transfer when the transfer
request is asserted and the number of transfers is set in the DMACA/TC registers. In this case,
DMACA/BC is set to "0".
In this mode, DMACA/BC values are ignored. DMACA/TC are decremented by 1 after the DMA
transfer has completed. DMA transfer therefore ends after the last transfer (TC is16'h0000) has
been completed.
Transfer gap
After completing 1 transfer, DMAC temporarily negates the bus request to the arbiter even
though the transfer request is asserted. This operation prevents the DMAC from blocking the bus.
This transfer gap can be used to update register settings (e.g. disable/interruption setting) to the
DMAC during DMA transfers.
Transfer request
External (DREQ) and peripheral (IDREQ) requests are permissible in demand transfer mode,
however software requests are prohibited.
• External request
Set "0" to DMACA/ST, and set 5'b01110 (H level of transfer request) or 5'b01111 (L level of
transfer request) to DMACA/IS
• Peripheral request
Set "0" to DMACA/ST, and set 5'b1**** (H level of transfer request) to DMACA/IS
When an external request or peripheral request is selected, the DMAC detects the transfer
request level.
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