Fujitsu MB86R02 Jade-D Hardware Manual page 870

MB86R02 'Jade-D' Hardware Manual V1.64
RSCK (pin DISP[j])
Register DIR_Pin_ctrl[j].Delay=0
RSDAT (pins DISP[i])
Registers DIR_Pin_ctrl[i].Delay=1
Pins TSIG[i]
Register Dir_SSwitch.SSwitch =0
Figure 34-2234-23, RSDS operation Output Timing
TTLCK (pin DISP[j])
Register DIR_Pin_ctrl[j].Delay=0
TTLDAT (pins DISP[i])
Registers DIR_Pin_ctrl[i].Delay=0
Register Dir_SSwitch.SSwitch =0
Figure 34-2434-25, TTL operation output timing (1)
TTLCK (pin DISP[j])
Register DIR_Pin_ctrl[j].Delay=0
Register DIR_Pin_Ctrl[j].Polarity=1
TTLDAT (pins DISP[i])
Registers DIR_Pin_ctrl[i].Delay=0
Register Dir_SSwitch.SSwitch =0
Figure 34-2634-27, TTL operation output timing (2)
RSCKH RSCKL
50%
RSSU RSHD
TSIGSU
TTLCKH
50%
DISPSU
TSIGSU
Pins TSIG[i]
TTLCKH
50%
DISPSU
TSIGSU
Pins TSIG[i]
RSSU RSHD
TSIGHD
TTLCKL
DISPHD
TSIGHD
TTLCKL
DISPHD
TSIGHD
diff.
0V diff.
TTL
34-31