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MB86R02 'Jade-D' Hardware Manual V1.64
13.6.8 DRAM CTRL SET TIME2 register (DRCST2)
This register sets access timing to DRAM. It should be set by the correlation between DRAM
spec and inner clock frequency.
Address
Bit
15
14
13
Name
-
R/W
R/W
Initial value
X
1
1
Bit field
No.
Name
15-12
(Reserved)
11-8
TRFC
7-6
(Reserved)
5-4
TRRD
3
(Reserved)
13-12
F300_0000
12
11
10
9
TRFC
R/W
0
1
0
1
Reserved bits.
Write access is ignored.
Auto. refresh command period (tRFC : Auto. refresh to active/Auto. refresh command
time )
Bit[11:8]
Cycle time (number of clock)
0000
4
0001
5
0010
6
0011
7
0100
8
0101
9
0110
10
0111
11
1000
12
1001
13
1010
14
1011
15
1100
16
1101
17
1110
18
1111
19
Reserved bits.
Write access is ignored.
RAS to RAS bank active delay time (tRRD : Active bank A to active bank B command
period)
Active command interval for when continuously activating RAS in different bank is set
in cycle.
Bit[5:4]
Cycle time (number of clock)
11
3
Others
-
Reserved bit.
Write access is ignored.
+ 0C
H
H
8
7
6
5
-
-
TRRD
R/W R/W
R/W
1
X
X
1
Description
(Initial value)
(Initial value)
Reserved (setting prohibited)
4
3
2
1
-
TWR
R/W
R/W
1
X
1
0
0
1
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